Computer Authentication using Hardware Intrinsic Security
With the ever-shrinking transistor size and the sheer increase in circuit complexity, the power dissipated by digital circuits has been growing exponentially. This situation leads to a degraded circuit reliability and a higher cost per unit due to elaborated cooling and packaging solutions. Another issue is the limited battery lifetime, especially for modern portable systems, which impose stringent demands upon the design. As a consequence, tools for power assessment are crucial to contemporary designs. Although SystemC is considered the most promising language for system-on-chip functional modeling, it doesn’t come with power modeling capabilities. PowerSC is a novel power estimation framework which instruments SystemC for power characterization, modeling and estimation. Its methodology is complementary to SystemC, with seamless integration to the current design flow. PowerSC integrates the power modeling of heterogeneous components of today’s complex SoCs, as for example IPs, busses, memories and processors into a single framework. Since it is entirely based on SystemC, PowerSC allows consistent power modeling from the highest to the lowest abstraction level. Besides, the framework’s API provides facilities to integrate alternative modeling techniques, either at the same or at different abstraction levels. As a result, the required power evaluation infrastructure is reduced to a minimum: the standard SystemC library, the PowerSC library itself and a C++ compiler. The power-conscious methodology has been carefully designed so as to make it as transparent as possible to the user, resulting in a minimum footprint left in the SystemC description. The main steps necessary for such task are the inclusion of the PowerSC’s main header file and the setting of some compiler directives in order to generate a power-aware executable specification. The system components are monitored throughout the simulation regarding their power consumption and the results are reported at simulation completion. The PowerSC framework also supports technology libraries in the Liberty format (.lib) format, in order to permit the power characterization step to be realized within the same SystemC environment, at the gate-level. The technology libraries are automatically converted to a C++ description so as to be compiled along with the SystemC description.
ArchC is an open-source architecture description language based on SystemC, a hardware description language that is receiving a strong support from many companies in the computer industry. Our goal in designing ArchC was to provide researchers with a powerful tool that can allow them to quickly evaluate new ideas in areas like: processor and ISA design, memory hierarchy and other aspects of computer architecture research. This project includes sub-projects like: acBinutils, acPower, acRtl.
The main goal of this project is to provide a complete simulation infrastructure based on SystemC with a hardware/software multiprocessor environment in order to facilitate the deployment, analysis and verification of new concepts, new tools and methodologies in the MPSoCs scenario. The MPSoCBench benchmark is a scalable set of MPSoC platforms composed by four different ArchC processor models (ARM, PowerPC, MIPS, and SPARC), IPs, communication devices and a representative set of application adapted from Splash-2, ParMibench, and MiBench benchmarks, which contains 844 different multicore configurations with up to 64 cores. The MPSoCBench fosters even more research and development on parallel software, power consumption profiling, hardware synthesis, and verification at higher abstraction levels.
The goal of this project is to study the problems involved in the detection and optimization of execution traces of hot sequential object code. Dynamic program execution has shown to be a rich environment where to collect program optimization information. The combination of such environment, with low-level virtual machines, has revealed new code optimization opportunities which are not available at compile time. This project aims at studying algorithms and techniques to unleash this potential.
As the complexity of embedded systems grows so does the difficulty of verifying such designs. System level descriptions like SystemC and SpecC have been proposed as a way to speed up system design and verification. Their goal is to enable executable specifications that can be gradually refined toward a final implementation. This project aims at the design of efficient algorithms and methodologies that can enable semi-automatic verification of high-level descriptions in SystemC.
Brazil-IP is a collaborative effort of Brazilian institutions to create a distributed network of integrated circuit (IC) design centers capable of delivering OCP-IP compliant Intellectual Property (IP cores). The mission of Brazil IP are twofold. In the short run, it aims at increasing the country expertise on designing world-class IC’s by exposing the participating centers to real-world design practices and evaluation. In the long-run, it seeks to enable the conditions for the establishment of local Design Houses (DH’s) capable of competing in the international IP market.
Reducing program size has become an important goal in the design of modern embedded systems target to mass production. This problem has driven a number of efforts aimed at designing processors with shorter instruction formats (e.g. ARM Thumb and MIPS16), or that are able to execute compressed code (e.g. IBM CodePack PowerPC). In this project we study new code compression techniques. Our approach has been validated for the MIPS and SPARC architectures. MicroLeon is the first FPGA implementation, which uses the Micro decompressor and the Leon SPARC V8 compliant core.
It is well known that performance gains in application execution can be obtained by synthesizing inner loops in hardware. However, only recently, with the advances in FPGA devices, it became possible to do that quickly and cheaply. The ChameLeon project aims at finding solutions to research problems related to the automatic synthesis of application inner loops into RISC datapaths. We focus on three main tasks: automation of loop extraction and synthesis, development of efficient algorithms for datapath merging and automatic generation of compilation tools.
The dramatic reduction in the cost of silicon area, and the big improvements in productivity due to automatic design tools, are gradually opening up the possibility for high-performance, very low-cost computation, as in portable and consumer electronics. The design of such devices has to satisfy stringent design constraints like high performance, low cost and low power consumption. In order to meet these requirements, architecture designers have to make better usage of the silicon through architectural specialization, improving performance, at the expense of increasing design complexity and programming difficulty. The main goal of this project is the design and implementation of a compiler that can support advanced research on compiling techniques for embedded and reconfigurable computing.
Virtual machines had proven to be very effective and versatile tools to solve or mitigate numerous problems in computer systems. Virtual machines are used in Instruction Set Architecture (ISA) Virtualization to enable compiled software to execute on systems with different architectures. They also allow multiple software systems to be executed on the same hardware platform, increasing system efficiency via resource sharing while maintaining security through system isolation.
The Virtual Machine Technology projects aim at investigating techniques to design safe and efficient virtual machines.
Dynamic Binary Code Optimizations
The goal of this project is to study the problems involved in the detection and optimization of execution traces of hot sequential object code. Dynamic program execution has shown to be a rich environment where to collect program optimization information. The combination of such environment, with low-level virtual machines, has revealed new code optimization opportunities which are not available at compile time. This project aims at studying algorithms and techniques to unleash this potential