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2016

Evaluating and Improving Thread-Level Speculation in Hardware Transactional Memories

Juan Salamanca, José Nelson Amaral and Guido Araujo
30th IEEE International Parallel & Distributed Processing Symposium (IPDPS), May 23-27, 2016, Chicago, USA.                  To Appear.

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2015

Study of Hardware Transactional Memory Characteristics and Serialization Policies on Haswell

Marcio Machado Pereira, Mathew Gaudet, José Nelson Amaral and Guido Araujo
Parallel Computing Journal (PARCO), December 2015.

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Open source platform for digital simulation, characterization and modeling attacks on delay based Physical Unclonable Functions (PUFs)

Rodrigo C. Surita, Mario L. Côrtes, Diego F. Aranha, Guido Araujo
XXIII Congresso de Iniciação Científica da Unicamp
Novembro 17-19, 2015, Campinas, Brasil.

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Using Hardware Transactional Memory to Enable Speculative Trace Optimization

Juan Salamanca, Jose Nelson Amaral and Guido Araujo
In 6th Workshop on Applications for Multi-Core Architectures, October 2015, Florianopolis, Brazil.

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Serialization Management for Best-Effort Hardware Transactional Memory: A key for performance

Matthew Gaudet, Jose Nelson Amaral and Guido Araujo
In 27th International Symposium on Computer Architecture and High Performance Computing (SBACPAD), October 2015, Florianopolis, Brazil.

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Computer Security by Hardware-Intrinsic Authentication

Caio Hoffman, Mario Cortes, Diego Aranha  and Guido Araujo
In International Conference on Hardware/Software Co-design and Synthesis (ISSS+CODES), October 2015, Amsterdam, Netherlands.

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Improving the Statistical Variability of Delay-based Physical Unclonable Functions

Jefferson Capovilla, Mario Cortes and Guido Araujo
In 28th Symposium on Integrated Circuits and Systems Design (SBCCI), August 2015, Salvador, Brazil.

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A Parallel Implementation of Molecular Packing using Xeon Phi Support

Leandro Zanotto, Leandro Martinez and Guido Araujo
At Escola Regional de Alto Desempenho de São Paulo (ERAD-SP), August 2015, São Paulo, Brazil.

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The Batched DOACROSS Loop Parallelization Algorithm

Divino Cesar and Guido Araujo
In 13th International Conference on High Performance Computing and Simulation (HPCS), July 2015, Amsterdam, Netherlands.

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SHRINK: Reducing the ISA Complexity via Instruction Recycling.

Alexandro Bruno Cardoso Lopes, Rafael Auler, Luiz Ramos, Edson Borin, Rodolfo Azevedo
In 42nd ACM/IEEE International Symposium on Computer Architecture (ISCA), pp. 311-332, June 2015, Portland, USA.

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Performance Implications of Dynamic Memory Allocators on Transactional Memory Systems.

Alexandro Baldassin, Edson Borin and Guido Araujo
In 20th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), pp. 87-96, February 2015, San Francisco, USA.

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2014

MPSoCBench: A toolset for MPSoC system level evaluation

Liana Duenha, Marcelo Guedes, Henrique Almeida and Rodolfo Azevedo. Org: 2014 International Conference on Embedded Computer Systems: Architectures, pp. 164-169, 2014

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Leveraging Optimization Methods for Dynamically Assisted Control-Flow Integrity Mechanisms

Moreira, J. B. C. G, Teixeira, L, Edson Borin and Sandro Rigo. . Em: 26th International Symposium on Computer Architecture and High Performance Computing, p. 1-6, 2014.

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LSQuiz:A Collaborative Classroom Response System to Support Active Learning Through Ubiquitous Computing

Ricardo Caceffo, Rodolfo Azevedo. Em: International Conference Cognition and Exploratory Learning in Digital Age, p. 63-71, 2014

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Fast and Accurate Solution for Power Estimation and DPA Countermeasure Design

Vidal, D,  Côrtes, M. L . Em: International Workshop on Power And Timing Modeling, 2014.

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Empirical and Analytical Approaches for Web Server Power Modelling

Leonardo Piga, Reinaldo Bergamaschi and Sandro Rigo
Cluster Computing. v. 1, p. 1-15,2014.

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Adaptive Global Power Optimization for Web Servers

Leonardo Piga, Reinaldo Bergamaschi, Maurício Breternitz and Sandro Rigo
Journal of Supercomputing. v. 1, p. 1-25, 2014.

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Measuring Effective Work to Reward Success in Dynamic Transaction Scheduling

Marcio Pereira, José Nelson Amaral and Guido Araujo
In 43rd International Conference on Parallel Processing (ICPP), September 9-12 2014, Minneapolis, USA

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Loop-Carried Dependence Verification in OpenMP

Juan Salamanca, Luis Mattos, and Guido Araujo
In 10th International Workshop on OpenMP (IWOMP 2014), pp. 87–102, September 28-30, 2014, Salvador, Brazil

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Multi-dimensional Evaluation of Haswell’s Transactional Memory Performance

Marcio Machado Pereira, Matthew Gaudet, José Nelson Amaral and Guido Araujo
In 26th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), October 22-24 2014, Paris, France

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Cloud-based OpenMP Parallelization Using a MapReduce Runtime

Rodolfo Wottrich, Rodolfo Azevedo and Guido Araujo
In 26th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), October 22-24 2014, Paris, France

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Wear-out analysis of Error Correction Techniques in Phase-Change Memory

Caio Hoffman, Luis Ramos, Rodolfo Azevedo and Guido Araujo
In Design, Automation and Test in Europe Conference and Exhibition (DATE), March 9-13 2014, Dresden, Germany

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On the Impact of Dynamic Memory Management on Software Transactional Memory Performance

Alexandro Baldassin, Edson Borin and Guido Araujo
In 9th ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), March 2, 2014, Salt Lake City, USA (Best Paper Candidate)

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2013

Improving the Modeling and Analysis of Error Correction Techniques for Phase-Change Memory

Caio Hoffman, Luiz E. Ramos, Rodolfo Azevedo and Guido Araujo.

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ISA Aging: A X86 case study

Bruno Lopes, Rafael Auler, Rodolfo Azevedo and Edson Borin. Em: Workshop on the Interaction amongst Virtualization, p. 1-6, 2013.

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Reavaliando a Eficiência Energética de Memória Transacional em Processadores Convencionais

João Carvalho, Alexandro Baldassin and Rodolfo Azevedo. Em: XIV Simpósio em Sistemas Computacionais – WSCAD-SSC, p. 1-6, 2013.

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Assessing Computer Performance with SToCS

Leonardo Piga, Gomes, G, Rafel Auler, Rosa, B, Sandro Rigo and Edson Borin. Em: 4th ACM/SPEC International Conference on Performance Engineering, p. 1-4, 2013.

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Extending decoupled software pipeline to parallelize Java programs

André Loureiro,João Paulo Porto and Guido Araújo
Software, Practice & Experience (Print). v. 43, p. 525-541, 2013

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Zombie memory: extending memory lifetime by reviving dead blocks

Azevedo, Rodolfo and Davis, John D. and Strauss, Karin and Gopalan, Parikshit and Manasse, Mark and Yekhanin, Sergey
In Proceedings of the 40th Annual International Symposium on Computer Architecture. p. 452–463. Tel-Aviv, Israel. 2013.

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Cache-Based Cross-Iteration Coherence for Speculative Parallelization

Andre Baixo, Joao Paulo Porto, Guido Araujo.
In IEEE International Conference on High Performance Computing 2013. Bangalore, India. 2013.

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Modeling Virtual Machines Misprediction Overhead

Divino Cesar, Rafael Auler, Rafael Dalibera, Sandro Rigo, Edson Borin and Guido Araujo.
International Symposium on Workload Characterization. 2013.

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An automatic energy consumption characterization of processors using ArchC

Marcelo Guedes, Rafael Auler, Liana Duenha, Edson Borin, Rodolfo Azevedo.
Journal of Systems Architecture . v. 59. p. 603 – 614. 2013.

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Transaction Scheduling Using Dynamic Conflict Avoidance

Daniel Nicácio, Alexandro Baldassin, Guido Araújo.
International Journal of Parallel Programming. v. 41. p. 89-110. 2013.

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Transaction Scheduling using Conflict Avoidance and Contention Intensity

Marcio Pereira, Alexandro Baldassin, Luiz Buzato, Guido Araujo.
In IEEE International Conference on High Performance Computing. Bangalore, India. 2013.

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2012

Compressing Variable-Length Instruction Traces

Zinsly, R., Sandro Rigo and Edson Borin.  Em: XIII Simpósio em Sistemas Computacionais (WSCAD-SSC’12), p. 1-8, 2012.

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Energy-Performance Tradeoffs in Software Transactional Memory

Alexandro Baldassin, João Carvalho, Leonardo Garcia and Rodolfo Azevedo.  Em: 2012 24th International Symposium on Computer Architecture and High Performance Computing (SBACPAD), p. 147-154, 2012

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ACCGen: An Automatic ArchC Compiler Generator

Rafael Auler, Paulo Cesar Centroducatte and Edson Borin. Em: 24th International Symposium on Computer Architecture and High Performance Computing, p. 278-285, 2012

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Optimizing Simulation in Multiprocessor Platforms using Dynamic-Compiled Simulation

Maxiwell Garcia, Rodolfo Azevedo and Sandro Rigo.  Em: 2012 13th Symposium on Computer Systems XIII Simp sio de Sistemas Computacionais (WSCADSSC), p. 80-6, 2012

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An ArchC approach for automatic energy consumption characterization of processors

Marcelo Guedes, Rafael Auler, Edson Borin and Rodolfo Azevedo.  Em: 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), p. 57-63, 2012.

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Asynchronous Program Flow Verification Through Binary Instrumentation on QEMU

Moreira, J. B. C. G., Lucas, D. C., Guido Araujo, Edson Borin and Sandro Rigo  Em: 5th Workshop on Architectural and Microarchitectural Support for Binary Translation, p. 1-8, 2012.

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Computational reflection and its application to platform verification

Bruno Albertini, Sandro Rigo, Guido Araujo.
Design Automation for Embedded Systems. v. 16. p. 1-17. 2012.

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A transactional runtime system for the Cell/BE architecture

Alexandro Baldassin, Felipe Goldstein, Rodolfo Azevedo.
Journal of Parallel and Distributed Computing . v. 72. p. 1535 – 1546. 2012.

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Energy-Performance Tradeoffs in Software Transactional Memory

A. Baldassin, J.P.L. de Carvalho, L.A.G. Garcia, R. Azevedo.
In Computer Architecture and High Performance Computing (SBAC-PAD), 2012 IEEE 24th International Symposium on. p. 147-154. 2012.

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Data center power and performance optimization through global selection of P-states and utilization rates

Reinaldo A. Bergamaschi, Leonardo Piga, Sandro Rigo, Rodolfo Azevedo, Guido Araújo.
Sustainable Computing: Informatics and Systems . v. 2. p. 198 – 208. 2012.

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Microcode Compression Using Structured-Constrained Clustering

Edson Borin, Guido Araujo, Jr. Mauricio Breternitz, Youfeng Wu.
International Journal of Parallel Programming. p. 1-25. 2012.

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Exploring Dynamic Program Behavior with Frames and Phases

D. Cesar, G. Araujo, E. Borin.
In Computer Systems (WSCAD-SSC), 2012 13th Symposium on. p. 118-125. 2012.

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Profiling High Level Abstraction Simulators of Multiprocessor Systems

Liana Duenha, Rodolfo Azevedo.
In Proceedings of the Second Workshop on Circuits and Systems Design – WCAS. 2012.

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Extending decoupled software pipeline to parallelize Java programs

André Loureiro, João Paulo Porto, Guido Araujo.
Software: Practice and Experience. p. 525–541. 2012.

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Transaction Scheduling Using Dynamic Conflict Avoidance

Daniel Nicácio, Alexandro Baldassin, Guido Araújo.
International Journal of Parallel Programming. p. 1-22. 2012.

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2011

Evaluation of Low Power Design Techniques on an MPEG2 Video Decoder Platform

Yang Yun Ju and Guido Araujo. Em: I Workshop on Circuits and System Design (WCAS), 2011, João Pessoa, Brazil

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Electronic System Level Design: An Open-Source Approach

Sandro Rigo , Rodolfo Azevedo and Luiz Santos. 1 ed. 0.

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Modeling, Simulation and Optimization of Power and Performance of Data Centers

Reinaldo Bergamaschi, Leonardo Piga, Rodolfo Azevedo, Sandro Rigo and Guido Araujo. Em: Workshop on Modeling, p. 1-6, 2011.

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Empirical Web Server Power Modeling and Characterization

Leonardo Piga, Reinaldo Bergamaschi, Klein, F., Rodolfo Azevedo and Sandro Rigo. Em: 2011 IEEE International Symposium on Workload Characterization, p. 1-4, 2011.

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Electronic System Level Design

Santos, L. C. V, Rigo, S, Azevedo, R. J and Araújo, G. Org: Sandro Rigo, Luiz Santos and Rodolfo Azevedo.  Electronic System Level Design. 1ed. 2011.p. 3-10.

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Open Source Languages

Rigo, S, Santos, L. C. V, Azevedo, R. J and Guido Araújo . Org: Sandro Rigo, Luiz Santos and Rodolfo Azevedo. Electronic System Level Design: An Open-Source Approach. 1ed. 2011.p. 11-24.

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SystemC-Based Power Evaluation with PowerSC

Klein, Felipe , Azevedo, R. J, Santos L.C.V, Guido Araújo. Org: Sandro Rigo, Luiz Santos and Rodolfo Azevedo. SystemC-Based Power Evaluation with PowerSC. 1ed. 2011.p. 129-144.

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Retargetable Binary Tools

Baldassin, A, Centoducatte, Paulo, Santos L. C.V, Org: Rigo, S, Rodolfo Azevedo, Santos, L.C.V. Electronic System Level Design: An Open-Source Approach. 1ed.Nova york. : Springe. 2011.p. 99-11

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Debugging SystemC Platform Models

Bruno Albertini, Rigo, Sandro, Guido Araújo, Org: Sandro Rigo, Luiz Santos and Rodolfo Azevedo.  Debugging SystemC Platform Models. 1ed. 2011.p. 117-128.

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Electronic System Level Design: An Open-Source Approach

Sandro Rigo, Rodolfo Azevedo and Luiz Santos 1 ed. 2011. v. 1. 155p.

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Ferramenta de apoio para o aprendizado ativo usando dispositivos com caneta eletrônica

Ricardo Caceffo , Heloísa Rocha, Rodolfo de Azevedo
Revista Brasileira de Informação na Educação. v. 19, p. 25-41, 2011

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Assessing the influence of data access patterns and contention management policies on the performance of software transactional memory systems

Fernando Kronbauer, Fernando André and Sandro Rigo
International Journal of High Performance Systems Architecture (Print). v. 3, p. 110,2011

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Software Co-Verification Based on Program Traces from Different Processors

Robledo Alencar, Sandro Rigo, Rodolfo Azevedo.
In 3rd Workshop on Infrastructures for Software/Hardware co-design – WISH. Charmonix, France. 2011.

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Live Range Hole Allocation in Dynamic Binary Translation

Wesley Attrot, Daniel Nicacio, Edson Borin, Sandro Rigo, Guido Araujo.
In 4th Workshop on Architectural and Microarchitectural Support for Binary Translation, AMAS-BT’11, 2011.. San Jose, USA. 2011.

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LAR-CC: Large Atomic Regions with Conditional Commits

Edson Borin, Youfeng Wu, Mauricio Breternitz Jr., Cheng Wang.
In Code Generation and Optimization (CGO), 2011 9th Annual IEEE/ACM International Symposium on. p. 54–63. 2011.

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Structure-Constrained Microcode Compression

Edson Borin, Guido Araujo, Mauricio Breternitz Jr., Youfeng Wu.
In 23rd Symposium on Computer Architecture and High Performance Computing. p. 104-111. 2011.

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Using multiple abstraction levels to speedup an MPSoC virtual platform simulator

J. Moreira, F. Klein, A. Baldassin, P. Centoducatte, R. Azevedo, S. Rigo.
In Rapid System Prototyping (RSP), 2011 22nd IEEE International Symposium on. p. 99 -105. 2011.

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LUTS: A Lightweight User-Level Transaction Scheduler

Daniel Nicácio, Alexandro Baldassin, Guido Araújo.
In Algorithms and Architectures for Parallel Processing. v. 7016. p. 144-157. 2011.

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A HW/SW Co-designed Heterogeneous Multi-core Virtual Machine for Energy-Efficient General Purpose Computing

Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang.
In Code Generation and Optimization (CGO), 010011 9th Annual IEEE/ACM International Symposium on. p. 236-245. 2011.

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2010

Automatic Architecture Description Language (ADL)-Based Toolchain Generation: The Dynamic Linking Framework

Rafael Auler,  Baldassin, A. and Centroducatte, P. C. Em: 14th Brazilian Symposium on Programming Languages (SBLP), p. 27-40, 2010.

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ViCOS Virtual Cluster Orchestration System

Kirst, R. , Baggio, H. and Sandro Rigo. Em: Conferencia Latino Americana de Computación de Alto Rendimiento, p. 1-6, 2010.

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ARP: Um Gerenciador de Pacotes para Sistemas Embarcados com Processadores Modelados em ArchC

Rodolfo Azevedo, Bruno Albertini, Sandro Rigo.
In Workshop de Sistemas Embarcados – WSE. Gramado. 2010. (In Portuguese)

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T-DRE: a hardware trusted computing base for direct recording electronic vote machines

Roberto Gallo, Henrique Kawakami, Ricardo Dahab, Rafael Azevedo, Saulo Lima, Guido Araujo.
In Proceedings of the 26th Annual Computer Security Applications Conference. p. 191–198. Austin, Texas. 2010.

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Optimizing a Retargetable Compiled Simulator to Achieve Near-Native Performance

M.S. Garcia, R. Azevedo, S. Rigo.
In 11th Symposium on Computing Systems (WSCAD-SCC). p. 33 -39. 2010.

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STM versus lock-based systems: an energy consumption perspective

Felipe Klein, Alexandro Baldassin, Joao Moreira, Paulo Centoducatte, Sandro Rigo, Rodolfo Azevedo.
In ISLPED ’10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design. p. 431–436. Austin, Texas, USA. 2010.

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Versatile system-level memory-aware platform description approach for embedded MPSoCs

Robert Pyka, Felipe Klein, Peter Marwedel, Stylianos Mamagkakis.
In LCTES ’10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems. p. 9–16. Stockholm, Sweden. 2010.

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Reducing False Aborts in STM Systems

Daniel Nicacio, Guido Araujo.
In Algorithms and Architectures for Parallel Processing. v. 6081. p. 499-510. 2010.

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Trace Execution Automata in Dynamic Binary Translation

Joao Porto, Guido Araujo, Edson Borin, Youfeng Wu.
3rd Workshop on Architectural and Microarchitectural Support for Binary Translation, AMAS-BT’10, 2010.. 2010.

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Integer-linear Formulation for the DAGs-packing Problem

Rubia Santos, Rodolfo Azevedo, Ricardo Santos.
In INFORMS Joint International Meeting Book of Abstracts. p. 34. 2010.

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ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation

Maxwell Souza, Daniel Nicarcio, Guido Araujo.
3rd Workshop on Architectural and Microarchitectural Support for Binary Translation, AMAS-BT’10, 2010.. 2010.

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2009

An execution model for Java on Cell BE Processor

Francisco Hoyos, Bruno Teles and Rodolfo Azevedo. Em: Simpósio Brasileiro de Linguagens de Programação – SBLP, p. 1-14, 2009.

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A general image processing architecture for FPGA

Fábio Cappabianco, Guido Araujo, Rodolfo Azevedo and Alexandre Falcão. Em: 5th Southern Conference on Programmable Logic, v. 1, p. 27-32, 2009

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Experimentos com Gerenciamento de Contenção em uma Memória Transacional com Suporte em Software

Fernando Kronbauer and Sandro Rigo. Em: X Simpósio em Sistemas Computacionais WSCAD-SSC, 2009.

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A Novel Verification Technique to Uncover Out-of-Order DUV Behaviors

Marcilio, G. , Santos, L. C. V. ,Bruno de Carvalho Albertini and sandro Rigo. Em: 46th ACM/IEEE Design Automation Conference, p. 448-453, 2009.

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Active Learning and Screencasting with Tablet PC: A detailed Evaluation

Pedro Almeida and Rodolfo Azevedo.  Em: Workshop on the Impact of Pen-Based Technology on Education, p. 1-6, 2009.

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Modelos mentais: um estudo de caso referente à introdução de computadores no ensino

Pedro Almeida and Rodolfo Azevedo.  Em: Workshop sobre Informática na Escola – WIE, p. 1-9, 2009.

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Slides Manager Tool: Supporting Active Learning Using Tablet PC and Pen-Based Devices

Ricardo Caceffo, Heloísa Rocha and Rodolfo Azevedo. Em: Workshop on the Impact of Pen-Based Technology on Education, p. 1-5, 2009.

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An Early Real-Time Checker for Retargetable Compile-Time Analysis

Wuerges, E. , Santos, L. C. V. , Furtado, O. J. V. and Sandro Rigo. Em: 22nd Symposium on Integrated Circuits and Systemsd Design, 2009.

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HW/SW co-design of Identity-Based Encryption using a custom instruction set

L. Amaral, G. Araujo, J. Lopez.
International Conference on Field-Programmable Technology, 2009. FPT 2009.. p. 510 -513. 2009.

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Um sistema de ligação dinâmica independente de arquitetura baseado em ADL

Rafael Auler, Paulo Cesar Centoducatte, Alexandro Baldassin.
Technical Report: Institute of Computing, University of Campinas. 2009. (In Portuguese)

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Dotando ArchC com infraestrutura para geração de montadores e simuladores ARM

Rafael Auler, Paulo Centoducatte.
In WSCAD-WIC ’09: X Simpósio em Sistemas Computacionais – Workshop de Iniciação Científica. São Paulo, Brazil. 2009. (In Portuguese)

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Characterizing the Energy Consumption of Software Transactional Memory

Alexandro Baldassin, Felipe Klein, Guido Araujo, Rodolfo Azevedo, Paulo Centoducatte.
Computer Architecture Letters. v. 8. p. 56-59. 2009.

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SPARC16: A New Compression Approach for the SPARC Architecture

Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo Candido Xavier, Ricardo Pannain, Paulo Centoducatte, Rodolfo Jardim de Azevedo.
In SBAC-PAD ’09: Proceedings of the 2009 21st International Symposium on Computer Architecture and High Performance Computing. p. 169–176. 2009.

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On the Energy-Efficiency of Software Transactional Memory

F. Klein, A. Baldassin, G. Araujo, P. Centoducatte, R. Azevedo.
In SBCCI ’09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design. p. 1–6. Natal, Brazil. 2009.

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A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization

F. Klein, R. Leao, G. Araujo, L. Santos, R. Azevedo.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. v. 17. p. 660 -673. 2009.

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Improving Accuracy in Power Estimation by Exploiting Multi-Model Techniques

Felipe Klein, Guido Araujo, Rodolfo Azevedo.
In VLSI-Soc 2009 (PhD Forum): Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (PhD Forum). 2009.

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Estimativa de Consumo de Energia em Nível de Instrução para Processadores Modelados em ArchC

Josue Ma, Rodolfo Azevedo.
In Workshop de Sistemas Computacionais – WSCAD-SSC. p. 119-126. São Paulo. 2009. (In Portuguese)

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Comparing RTL and high-level synthesis methodologies in the design of a theora video decoder IP core

L. Piga, S. Rigo.
Programmable Logic, 2009. SPL. 5th Southern Conference on. p. 135 -140. 2009.

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A pattern based instruction encoding technique for high performance architectures

Ricardo Santos, Rafael Batistella, Rodolfo Azevedo.
International Journal of High Performance Systems Architecture. v. 2. p. 71-80. 2009.

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2008

Processor Design with ArchC

Guido Araujo, Sandro Rigo and Rodolfo Azevedo.  Org: Prabhat Mishra; Nikil Dutt. Processor Description Languages. 1ed.San Francisco. : Morgan Kaufmann. 2008.v. 1, p. 275-294

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An Open-Source Binary Utility Generator

Alexandro Baldassin, Paulo Cesar Centroducatte, Sandro Rigo, Daniel Casarotto, Luís Santos, Max Schultz and Olinto Furtado
ACM Transactions on Design Automation of Electronic Systems. v. 13, p. 27-1-27-17, 2008

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 Cold Code Analysis

Wesley Attrot.
In AMAS-BT: Proceedings of 1th Workshop on Architectural and Microarchitectural Support for Binary Translation. p. 14-21. Beijing, China. 2008.

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PBIW: Uma Codificação de Instruções Alternativa para Arquiteturas de Alto Desempenho

Rafael Batistella, Ricardo Santos, Rodolfo Azevedo.
In WSCAD-SSC Simpósio em Sistemas Computacionais. p. 151-158. 2008.

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Design, Implementation and Evaluation of two MP3 Hardware Decoder in Different Abstraction Levels using SystemC

F. Goldstein, R. Azevedo.
In Design & Verification Conference. San Jose, CA, USA. 2008.

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A Software Transactional Memory System for an Asymmetric Processor Architecture (Best Paper Award)

Felipe Goldstein, Alexandro Baldassin, Paulo Centoducatte, Rodolfo Azevedo, Leonardo A. G. Garcia.
In SBAC-PAD ’08: Proceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing. p. 175–182. 2008.

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Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor

R. Santos, R. Azevedo, G. Araujo.
Journal of Universal Computer Science. v. 14. p. 3465–3480. 2008.

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An Instruction Scheduling Algorithm Based on Subgraph Isomorphism

R. Santos, R. Azevedo.
In Simpósio Brasileiro de Linguagens de Programação. Fortaleza, CE, Brasil. 2008. (In Portuguese)

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2007

A Computational Reflection Mechanism to Support Platform Debugging in SystemC

Bruno de Carvalho Albertini, Sandro Rigo, Guido Araújo, Cristiano Araújo, Edna Barros and Azevedo, W. Em: International Conference on Hardware – Software Codesign and System Synthesis (CODES+ISSS), p. 81-86, 2007.

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The Image Forest Transform Architecture

Cappabianco, F. , Guido Araujo and Alexandre Falcão  Em: IEEE Intl. Conf. on Field Programmable Technology (ICFPT),, v. 1, p. 137-144, 2007

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A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F_(2^163) using Gaussian Normal Bases

Marcio Juliato, Guido Araújo, Julio Lopez, Ricardo Dahab
Journal of VLSI Signal Processing. v. 47, p. 59-76, 2007.

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Automatic Retargeting of Binary Utilities for Embedded Code Generation

Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel Casarotto, Luiz C. V. Santos, Max Schultz, Olinto Furtado.
In ISVLSI ’07: Proceedings of the IEEE Computer Society Annual Symposium on VLSI. p. 253–258. 2007.

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A Multi-Model Power Estimation Engine for Accuracy Optimization

Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz Santos.
In ISLPED ’07: Proceedings of the 2007 international symposium on Low power electronics and design. p. 280–285. Portland, OR, USA. 2007.

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On the Limitations of Power Macromodeling Techniques

Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. Dos Santos.
In ISVLSI 2007: Proceedings of the IEEE Computer Society Annual Symposium on VLSI. p. 395-400. 2007.

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An Efficient Framework for High-Level Power Exploration

F. Klein, G. Araujo, R. Azevedo, R. Leao, dos Luiz Santos.
In MWSCAS 2007: Proceedings of the 50th Midwest Symposium on Circuits and Systems. p. 1046-1049. 2007.

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PowerSC: A SystemC Framework for Power Estimation

F. Klein, G. Araujo, R. Azevedo.
In 6th NASCUG, San Jose, USA. 2007.

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PowerSC: A SystemC-based Framework for Power Estimation

Felipe Klein, Roberto Leao, Guido Araujo and Luiz Santos, Rodolfo Azevedo.
Technical Report: Institute of Computing, University of Campinas. 2007.

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A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation

Fernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo.
In RSP ’07: Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping. p. 123–129. 2007.

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A Methodology and Toolset to Enable SystemC and VHDL Co-simulation

Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo.
VLSI, IEEE Computer Society Annual Symposium on. v. 0. p. 351-356. 2007.

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A DAGs-Packing Heuristic for a High Performance Processor Architecture

Ricardo Santos, Rodolfo Azevedo, Rubia Oliveira.
In XXXIX Simpósio Brasileiro de Pesquisa Operacional. 2007.

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2006

Ipzip – An IP Distribution Framework

Cristiano Araujo, Edna Barros, Gomes, M. And Guido Araujo . Em: IP/SoC, 2006.

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Uma Nova Abordagem para um Curso de Projeto de Sistemas Computacionais.

Sandro Rigo, Rodolfo Azevdo, Paulo César Centroducatte, Guido Araújo. Em: Workshop sobre Educação em Arquitetura de Computadores (WEAC) – Em conjunto com o 18th International Symposium on Computer Architecture and High Performance Computing, 2006

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Silicon Validated IP Cores Designed by the Brazil-IP Network

Rocha, K., Lira, P., Yun Ju, Y. , Melcher, E. , Edna Barros and Guido Araujo. Em: IP/SoC 2006, 2006.

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Offset Assignment Using Simultaneous Variable Coalescing

Desiree Ottoni, Guilherme Ottoni, Guido Araújo and Rainer Leupers.
ACM Transactions on Embedded Computing Systems. v. 5, p. 864-883,2006

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A SystemC-only Design Methodology and the CINE-IP Multimedia Platform

Guido Araujo, Rodolfo Azevedo, Edna Barros, Manoel Lima, Bruno Prado, Elmar Melcher and Karina Silva.
Design Automation for Embedded Systems. v. 10, p. 181-202, 2006

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Projeto e Desenvolvimento de Sistemas Embarcados Multiprocessados

Rodolfo Azevedo, Sandro Rigo, Guido Araujo.
Atualizações em Informática. p. 331 -386. 2006. (In Portuguese)

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Software-Based Transparent and Comprehensive Control-Flow Error Detection

Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo.
In CGO ’06: Proceedings of the International Symposium on Code Generation and Optimization. p. 333–345. 2006.

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Clustering-Based Microcode Compression

E. Borin, M. Breternitz, Youfeg Wu, G. Araujo.
International Conference on Computer Design, 2006. ICCD 2006. p. 189 -196. 2006.

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2D-VLIW: An Architecture Based on the Geometry of Computation

Ricardo Santos, Rodolfo Azevedo, Guido Araujo.
International Conference on Application-specific Systems, Architectures and Processors, 2006. ASAP ’06. p. 87 -94. 2006.

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Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach

R. Santos, R. Azevedo, G. Araujo.
20th International Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. p. 4 pp.. 2006.

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The 2D-VLIW Architecture

Ricardo Santos, Rodolfo Azevedo, Guido Araujo.
Technical Report: Institute of Computing, University of Campinas. 2006.

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Dual Selective Code Compression

Eduardo Bráulio Wanderley Netto, Eduardo Billo, Rodolfo Jardim Azevedo.
XXXII Conferência Latino Americana de Informática, 2006. 2006.

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2005

P-CMM e outros modelos na Gestão de Pessoas

Côrtes, M. L. and João Marcelo Borovina Bosko. Em: SIMPROS 2005 – VII Simpósio Internacional de Melhoria de Processos de Software, 2005.

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Do SQA ao PPQA: a implementação CMMI do CPqD

Côrtes, M. L., André Villaboas and Sílvia Lopes. Em: SIMPROS 2005 – VII Simpósio Internacional de Melhoria de Processos de Software, 2005.

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Processor Centric Specification and Modelling of MPSoCs

Cristiano C. de Araujo and Edna Barros and Rodolfo Azevedo and Guido Araujo.
In Forum on specification and Design Languages. p. 303-315. 2005.

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Platform designer: An approach for modeling multiprocessor platforms based on SystemC

Cristiano Araujo, Millena Gomes, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo.
Design Automation for Embedded Systems. v. 10. p. 253-283. 2005.

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A SystemC-only design methodology and the CINE-IP multimedia platform

Guido Araújo, Edna Barros, Elmar Melcher, Rodolfo Azevedo, Karina Silva, Bruno Prado, Manoel Lima.
Design Automation for Embedded Systems. v. 10. p. 181-202. 2005.

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The ArchC Architecture Description Language and Tools

Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Araujo, Guido, Cristiano Araujo, Edna Barros.
International Journal of Parallel Programming. v. 33. p. 453-484. 2005.

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Extending the ArchC language for automatic generation of assemblers

A. Baldassin, P.C. Centoducatte, S. Rigo.
17th International Symposium on Computer Architecture and High Performance Computing. SBAC-PAD 2005. . p. 60 – 67. 2005.

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Geração Automática de Montadores para Modelos de Arquiteturas Escritos em ArchC

A. Baldassin, P.C. Centoducatte.
In Proceedings of the 9th Brazilian Symposium on Programming Languages. p. 36 – 49. 2005.

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Design of a Decompressor Engine on a SPARC Processor

E. Billo, R. Azevedo, G. Araujo, P. Centoducatte, E.W. Netto.
18th Symposium on Integrated Circuits and Systems Design. p. 110 -114. 2005.

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Dynamic binary control-flow errors detection

Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo.
SIGARCH Comput. Archit. News. v. 33. p. 15–20. 2005.

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A custom instruction approach for hardware and software implementations of finite field arithmetic over F2163 using Gaussian normal bases

M. Juliato, G. Araujo, J. Lopez, R. Dahab.
IEEE International Conference on Field-Programmable Technology. p. 5 – 12. 2005.

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High-Level Switching Activity Prediction Through Sampled Monitored Simulation

F. Klein, R. Azevedo, G. Araujo.
International Symposium on System-on-Chip, 2005. p. 161 -166. 2005.

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Enabling High-Level Switching Activity Estimation using SystemC

F. Klein, R. Azevedo, G. Araujo.
Technical Report: Institute of Computing, University of Campinas. 2005.

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Efficient datapath merging for partially reconfigurable architectures

N. Moreano, E. Borin, Cid de Souza, G. Araujo.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. v. 24. p. 969 – 980. 2005.

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The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation

Cid C. de Souza, Andre M. Lima, Guido Araujo, Nahri B. Moreano.
J. Exp. Algorithmics. v. 10. p. 2.2. 2005.

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Exploiting the Area X Performance Trade-off with Code Compression

E.W. Netto, E. Billo, R. Azevedo.
International Symposium on System-on-Chip, 2005. p. 42 -45. 2005.

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2004

Optimizations for compiled simulation using instruction type information

M. Bartholomeu, R. Azevedo, S. Rigo, G. Araujo.
In Computer Architecture and High Performance Computing, 2004. SBAC-PAD 2004. 16th Symposium on. p. 74 – 81. 2004.

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Fast Instruction Set Customization

E. Borin, F. Klein, N. Moreano, R. Azevedo, G. Araujo.
In ESTImedia 2004: Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia. p. 53-58. 2004.

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Looking for Instruction Patterns in the Design of Extensible Processors

Paulo Castro, Edson Borin, Rodolfo Azevedo, Guido Araujo.
In Workshop on Application Specific Processors – WASP’04. 2004.

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The design of dynamically reconfigurable datapath coprocessors

Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo.
ACM Trans. Embed. Comput. Syst.. v. 3. p. 361–384. 2004.

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ArchC: a systemC-based architecture description language (Best Paper Award)

S. Rigo, G. Araujo, M. Bartholomeu, R. Azevedo.
In 16th Symposium on Computer Architecture and High Performance Computing, 2004 – SBAC-PAD 2004. p. 66 – 73. 2004.

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Teaching computer architecture using an architecture description language

Sandro Rigo, Marcio Juliato, Rodolfo Azevedo, Guido Araujo, Paulo Centoducatte.
In Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture. Munich, Germany. 2004.

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An automatic testbench generation tool for a systemC functional verification methodology

K.R.G. da Silva, E.U.K. Melcher, G. Araujo.
In 17th Symposium on Integrated Circuits and Systems Design, 2004 – SBCCI 2004. p. 66 – 70. 2004.

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The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation

Cid C. de Souza, André M. Lima, Nahri Moreano, Guido Araujo.
In Experimental and Efficient Algorithms. v. 3059. p. 545-558. 2004.

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Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology

Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo.
In Proceedings of the conference on Design, automation and test in Europe – Volume 1. p. 10734–. 2004.

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Multi-profile based code compression

E. Wanderley Netto, R. Azevedo, P. Centoducatte, G. Araujo.
In Proceedings of the 41st annual Design Automation Conference. p. 244–249. San Diego, CA, USA. 2004.

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Multi-profile instruction based compression

E.W. Netto, R. Azevedo, P. Centoducatte, G. Araujo.
In 16th Symposium on Computer Architecture and High Performance Computing, 2004 – SBAC-PAD 2004. p. 23 – 29. 2004.

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2003

Comparing SystemC and ArchC through the MIPS Processor Modeling

Juliato, M. R. and Centroducatte, P.  Em: Student Forum on Microelectronics, 2003.

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Xingó: Prototyping Platform

Juliato, M. R. and Centroducatte, P. Em: Student Forum on Microelectronics, 2003.

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Emulating Operating System Calls in Retargetable ISA Simulators

Marcus Bartholomeu, Sandro Rigo and Rodolfo Azevedo, Guido Araujo.
Technical Report: Institute of Computing, University of Campinas. 2003.

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Address register allocation for arrays in loops of embedded programs

Guilherme Ottoni, Guido Araujo.
Microelectronics Journal. v. 34. p. 1009 – 1018. 2003.

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Improving Offset Assignment through Simultaneous Variable Coalescing (Best Paper Award)

Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers.
In Software and Compilers for Embedded Systems. v. 2826. p. 285-297. 2003.

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The ArchC Architecture Description Language

Sandro Rigo, Rodolfo J. Azevedo, Guido Araujo.
Technical Report: Institute of Computing, University of Campinas. 2003.

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Exploring memory hierarchy with ArchC

P. Viana, E. Barros, S. Rigo, R. Azevedo, G. Araujo.
In 15th Symposium on Computer Architecture and High Performance Computing, 2003. p. 2 – 9. 2003.

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Mixed static/dynamic profiling for dictionary based code compression

E. Netto, R. Azevedo, P. Centoducatte, G. Araujo.
In International Symposium on System-on-Chip, 2003. p. 159 – 163. 2003.

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2002

Comércio Eletrônico: uma Análise da Aplicabilidade de Modelos de Qualidade de Software

Côrtes, M. L. and Luiz Alberto Gomes. Em: I Simpósio Brasileiro de Qualidade de Software, v. 1, p. 100-115, 2002.

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Suitability of Software Quality Models to E-Commerce Applications.

Côrtes, M. L. and Luiz Alberto Gomes. Em: IADIS International Conference WWW/INTERNET 2002, v. 1, p. 632-635, 2002.

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Global array reference allocation

Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra.
ACM Trans. Des. Autom. Electron. Syst.. v. 7. p. 336–357. 2002.

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Datapath merging and interconnection sharing for reconfigurable architectures

Nahri Moreano, Guido Araujo, Zhining Huang, Sharad Malik.
In Proceedings of the 15th international symposium on System Synthesis. p. 38–43. Kyoto, Japan. 2002.

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Efficient Array Reference Allocation for Loops in Embedded Processors

Guilherme Ottoni, Guido Araujo.
In 1st IEEE Workshop on Embedded System Codesign. p. 63–68. 2002.

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2001

Uma avaliação CMM de baixo custo: a abordagem do CPqD

Côrtes, M. L. Em: Workshop de Qualidade de Software – SBC, p. 51-61, 2001.

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Using the IMPACT Compiler Framework to Implement a Compiler for a Fixed-Point DSP

Rajagapolan, S. , Rajan, S. , Malik, S. , Guido Araujo and Sandro Rigo. Em: 5th International Workshop on Software and Compilers for Embedded Systems, p. 285-297, 2001.

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Modelos de Qualidade de Software

Mário Lúcio Côrtes and Thelma Santos Chiossi.  1 ed. 2001. v. 3000. 150p .

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Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures

Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo.
In Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems. p. 141–148. Atlanta, Georgia, USA. 2001.

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Array Reference Allocation Using SSA-Form and Live Range Growth

Marcelo Cintra, Guido Araujo.
In Languages, Compilers, and Tools for Embedded Systems. v. 1985. p. 48-62. 2001.

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Optimal Live Range Merge for Address Register Allocation in Embedded Programs

Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik.
In Compiler Construction. v. 2027. p. 274-288. 2001.

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Modifying a VLIW Compiler Framework to Implement an Optimizing Compiler for a Fixed Point DSP

S. Rajagopalan, S.P. Rajan, S. Malik, S. Rigo, G. Araujo, S. Rajan.
In Proc. of the 5th International Workshop on Software and Compilers for Embedded Systems. v. 2027. p. 1-5. 2001.

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A retargetable VLIW compiler framework for DSPs with instruction-level parallelism

S. Rajagopalan, S.P. Rajan, S. Malik, S. Rigo, G. Araujo, K. Takayama.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. v. 20. p. 1319 -1328. 2001.

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2000

Arquiteturas Avançadas de Computadores: Uma Introdução

Centroducatte, P.  Em: 1a Jornada de Estudos em Computação de Piracicaba e Região, p. 135-153, 2000.

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Byte-Code Compression Using Abstract Syntax Tree Recovery

Costa, B. K. and Guido Araújo.  Em: 4th Symposium on Programming Languages, p. 15-23, 2000.

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Expression-tree-based algorithms for code compression on embedded RISC architectures

G. Araujo, P. Centoducatte, R. Azevedo, R. Pannain.
IEEE Transactions onVery Large Scale Integration (VLSI) Systems. v. 8. p. 530 -533. 2000.

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1999

Implantação CMM: a Experiência do CPqD

Côrtes, M. L. , Marta R. Bastos and André Villaboas. Em: X Conferência Internacional de Tecnologia de Software (CITS), 1999.

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Compressed code execution on DSP architectures

P. Centoducatte, G. Araujo, R. Pannain.
In 12th International Symposium onSystem Synthesis, 1999. p. 56 -61. 1999.

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Using Factorization to Compress DSP Programs

Ricardo Pannain, Paulo Centoducatte, Guido Araujo.
In 11th SBAC-PAD. p. 223-229. 1999.

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1998

Introdução ao teste de sistemas digitais

Côrtes, M. L. Em: International Conference on Microelectronics and Packaging, 1998.

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Avaliação CMM: a Experiência do CPqD

Côrtes, M. L, André Villaboas , Marta R. Bastos and Nazareth Arruda . Em: Workshop de Qualidade de Software – SBC, 1998.

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Code compression based on operand factorization

G. Araujo, P. Centoducatte, M. Cortes, R. Pannain.
In 31st Annual ACM/IEEE International Symposium on Microarchitecture, 1998. MICRO-31.. p. 194 -201. 1998.

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Code generation for fixed-point DSPs

Guido Araujo, Sharad Malik.
ACM Trans. Des. Autom. Electron. Syst.. v. 3. p. 136–161. 1998.

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1997

A FPGA Implementation of a Neighbourhood Processor for Digital Image Applications

Côrtes, M. L,  Alexandro dos Santos Adário and Neucimar José Leite. Em: X Simpósio Brasileiro de Concepção de Circuitos Integrados, 1997.

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Code Generation Algorithms for Digital Signal Processors

Guido Araujo.
In PhD Thesis. Princeton University. 1997.

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1996

Considerações sobre a Síntese em FPGAs de Células de Processadores Matriciais

Côrtes, M. L. and Alexandro dos Santos Adário. Em: XXIII Seminário Integrado de Software e Hardware – SEMISH, 1996.

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RemX – Uma Ferramenta para Execução de Aplicações Remotas voltada para a Integração de Ambientes Multi-Plataforma

Roberto Cordeiro, Rodolfo Azevedo and João Almeida.  Em: II WAIS – Workshop de Administração e Integração de Sistemas, 1996.

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Using register-transfer paths in code generation for heterogeneous memory-register architectures (Best Paper Award)

Guido Araujo, Sharad Malik, Mike Tien-Chien Lee.
In Proceedings of the 33rd annual Design Automation Conference. p. 591–596. Las Vegas, Nevada, United States. 1996.

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Instruction set design and optimizations for address computation in DSP architectures

G. Araujo, A. Sudarsanam, S. Malik.
In 9th International Symposium onSystem Synthesis. p. 102 -107. 1996.

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Code Generation and Optimization Techniques for Embedded Digital Signal Processors

Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang, Guido Araujo, Ashok Sudarsanam, Sharad Malik, Vojin Zivojnovic, Heinrich Meyr.
In First SUIF Workshop. 1996.

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1995

Challenges in Code Generation For Embedded Processors

G. Araujo, S. Devadas, K. Keutzer, S. Liao, S. Malik, A. Sudarsanam, S. Tjiang, A. Wang.
In Code Generation for Embedded Processors. 1995.

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Optimal code generation for embedded memory non-homogeneous register architectures

G. Araujo, S. Malik.
In Proceedings of the Eighth International Symposium on System Synthesis. p. 36 -41. 1995.

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1993

Uma Implementação em VLSI para o Reconhecimento de ImagemCôrtes, M. L.  Em: VI Conferência Nacional de Inteligência Artificial, 1993. Abstract
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Uma Implementação em VLSI para WisardCôrtes, M. L and Josemir Cruz Alexandrino. Em: Workshop sobre Computação de Alto Desempenho para Processamento de Sinais, 1993. Abstract
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Uma Implementação em VLSI para o Reconhecimento de ImagensCôrtes, M. L and Josemir Cruz Alexandrino. Em: XX Seminário Integrado de Software e Hardware, 1993. Abstract
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1991

Planejamento de EDA: a Experiência do CPqD

Côrtes, M. L. Em: VI Congresso da Sociedade Brasileira de Micro-Eletrônica, 1991.

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Introdução ao Teste de Circuitos Digitais

Mário Lúcio Côrtes and Jose de Mendonça Furtado Neto . Rio de Janeiro: V Escola Brasileiro-Argentina de Informática. 1991. v. 500. 140p.

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1990

Bidimensional simulation of MOSFETs in thermal equilibrium

Guido Araujo, Petronio Pulino, Bernard Waldman.
In The Intrnational Society for Optical Engineering. v. 1405. p. 26-35. 1990.

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1989

PLAs: Geração de Padrão de Teste e Avaliação de cobertura

Côrtes, M. L. and  A. J. L. Ribeiro.  Em: IV Congresso da Sociedade Brasileira de Micro-Eletrônica, 1989.

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H-ALG: um Algoritmo Hierárquico para a Geração de Padrão de Teste

J. M. Furtado Neto, and Côrtes, M. L.  Em: IV Congresso da Sociedade Brasileira de Micro-Eletrônica, 1989.

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1988

 I-ALG: um Algoritmo para a Geração de Padrão de Teste

Côrtes, M. L. and  J. M. Furtado Neto. Em: III Congresso da Sociedade Brasileira de Micro-Eletrônica, 1988

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1987

Robust Dynamic Recovery Mechanisms

Amer, H. and Côrtes, M. L. . Em: IEEE International Conference on Computer Design, 1987.

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1986

Um Sistema de Aquisição de Dados Meteorológico Baseado em Microprocessador

Centroducatte, P. , Gimenes, I. M. S. ,  Machado, N. C. and Pinto, H. H.  Em: I Semana de Informática da UFBA, 1986

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Modeling Power Supply Disturbances in Digital Circuits

Côrtes, M. L and McCluskey, E. J..  Em: IEEE International Solid State Circuits Conference, p. 164-165, 1986

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Properties of Transient Errors Due to Power Sypply Disturbances

Côrtes, M. L and McCluskey, E. J..  Em: IEEE International Symposium on Circuits and Systems, p. 1046-1049, 1986

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An Experiment on Intermittent-Failure Mechanisms

Côrtes, M. L and McCluskey, E. J..  Em: IEEE International Test Conference, 1986.

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1984

Device Failures and System Activity: a Thermal Effects Model

Côrtes, M. L and  Iyer, R. K..  Em: IEEE Fault Tolerant Computing Symposium, p. 71-76, 1984.

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